The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, lithography processes often implement exposing and developing processes to pattern small features during IC wafer fabrication and mask fabrication. One of the challenges that arise during the lithography processes is that latent pattern resist profiles formed by the exposing process have different polarity at different portions of the resist profiles. Such polarity differences are caused by light scattering and reflecting at the top and the bottom of a resist film during the exposing process. The different portions of the different polarity have a different solubility to an organic solvent developer used during the developing process, oftentimes resulting in a resist pattern profile with top scum (T-top) and bottom scum (footing).
Accordingly, what is needed is an apparatus and a method that address the above issues.